Discussion:
Linux on System z (IFL)
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adarsh khanna
2013-10-26 02:28:36 UTC
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Hi,

I am starting to learn about Linux on System z and was going through redbooks and other material available on IBM website as well as on google to get details on how is a mainframe core characterised as IFL.

For IFL, I came across "This is a normal processor with one or two instructions disabled that are used only by z/OS".
Please can someone help me understand :

1) Is the disabling of instructions done via micro or millicode?
2) How does diabling few instructions restrict z/OS from running on IFL?
3) Each mainframe book has MCM (multi chip module) which has 6 chips (latest version) and each chip has 6 cores - when characterising each core as IFL is it possible to have only 4 cores in a chip as IFL OR is it possible to have 2 cores from 1 chip and 2 cores from 2nd chip as IFL?
4) Once the system definition is complete and is executing production workloads, how is an IFL added to the system using the same book?

Thanks
Adarsh Khanna

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R.S.
2013-10-26 22:58:56 UTC
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Hi,
I am starting to learn about Linux on System z and was going through redbooks and other material available on IBM website as well as on google to get details on how is a mainframe core characterised as IFL.
For IFL, I came across "This is a normal processor with one or two instructions disabled that are used only by z/OS".
1) Is the disabling of instructions done via micro or millicode?
I don't know.
2) How does diabling few instructions restrict z/OS from running on IFL?
3) Each mainframe book has MCM (multi chip module) which has 6 chips (latest version) and each chip has 6 cores - when characterising each core as IFL is it possible to have only 4 cores in a chip as IFL OR is it possible to have 2 cores from 1 chip and 2 cores from 2nd chip as IFL?
Well, not every mainframe has MCM, not every PU is six-core, but every
processor you paid for can be characterized independently. So, you can
have any mix of CPs, IFLs you want (assuming not marketing
restrictions). BTW: you don't decide which core is CP, which core
remains not activated, etc. This is up to IBM, you decide (and pay) for
number of given processor types.
4) Once the system definition is complete and is executing production workloads, how is an IFL added to the system using the same book?
Well, "adding procesor" usually means activation of existing core. It
can be non-disruptive and concurrent. One term means no machine outage,
the second means the *properly configured* system, which has relevant
capabilities (like z/OS) is able to start using such processor without
reIPL. IFL can be added dynamically to z/VM, I don't know whether Linux
can start using new IFL without restart.
BTW: you can usually add new BOOK non-disruptively (few exceptions apply).

So, you can add any processor type you want to the machine and at least
some operating systems can start using it wihtout any outage. It's just
a matter of few bucks ;-)

BTW: You mentioned IFL and I mentioned CPs. You can also buy zIIPs,
zAAPs, ICFs and (rarely needed) additional SAPs. You already have some
SAPs built in, you also have some spare processors (at least 2 for big
"EC" machines). There are also "uncharacterized" cores - those you
didn't paid for.
You cannot pay for more spares, you usually don't need more SAPs (unless
you use z/TPF), but you can buy more "processors you didn't pay for" -
strange, but true: you can buy 2-BOOK configuration with very few
processors active. In such case you would get 1 BOOK, but you paid for
the second to have redundant configuration of better scalability.

HTH
--
Radoslaw Skorupka
Lodz, Poland






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Jon Perryman
2013-10-26 23:20:17 UTC
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I can't tell you the specifics about IFL's. I don't think it really matters but I could be wrong.  Z machines have multiple CPU's that are the same. You can pay for the CPU's you want to use in the box. IBM disables those that you don't pay for. As an incentive to buy z architecture, IBM will allow you to pay a reduced rate for some (not all) processors E.g. IFL, zAAP, zIIp and ICF. IBM calls these specialized processors and they only allow the specific workload type.

As for disabling instructions, I don't think it restricts z/OS. It probably makes z/OS unusable when running on that CPU. If you somehow get z/OS onto an IFL, then it will most likely fail. Just a method to force you into paying for what you use. 

It's been many year's since I actually did anything with hardware so I don't know how CPU's are allocated any more. I thought that LPAR management doesn't allow you to specify specific CPU's. I thought you simply specified xx% of x IFL CPU's and xx% of 2 CP CPU's.

As for adding / reconfiguring CPU's, I think IBM can do this remotely with a dialup to your machine.

Jon Perryman.


----- Original Message -----
Post by adarsh khanna
 
I am starting to learn about Linux on System z and was going through redbooks
and other material available on IBM website as well as on google to get details
on how is a mainframe core characterised as IFL.
For IFL, I came across "This is a normal processor with one or two
instructions disabled that are used only by z/OS".
1) Is the disabling of instructions done via micro or millicode?
2) How does diabling few instructions restrict z/OS from running on IFL?
3) Each mainframe book has MCM (multi chip module) which has 6 chips (latest
version) and each chip has 6 cores - when characterising each core as IFL is it
possible to have only 4 cores in a chip as IFL OR is it possible to have 2 cores
from 1 chip and 2 cores from 2nd chip as IFL?
4) Once the system definition is complete and is executing production workloads,
how is an IFL added to the system using the same book?
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Mark Post
2013-10-27 06:02:40 UTC
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-snip0
Post by adarsh khanna
1) Is the disabling of instructions done via micro or millicode?
Most likely millicode, but it could be microcode.
Post by adarsh khanna
2) How does diabling few instructions restrict z/OS from running on IFL?
IBM makes sure that z/OS (and z/TPF and z/VSE) executes that instruction during early IPL processing. If that is on an IFL, the entire LPAR will experience a check stop.


Mark Post

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