Discussion:
Cross-memory POST ERRET and return codes
(too old to reply)
Charles Mills
2018-10-08 22:41:11 UTC
Permalink
Pursuant to a recent thread here I am converting a cross-memory POST to use
IEAMSXMP instead. However ... I still need to support older systems without
IEAMSXMP support, so I will be dual-pathing the existing POST. I got to
looking at code that I have not examined in several years, and I am trying
to determine exactly what is or should be going on. It runs without apparent
errors, so this is kind of a theoretical question, not "please help me with
this error." Here's the POST

POST (R3),LINKAGE=BRANCH,ASCB=(R2),ERRET=POSTERR,MEMREL=NO

The questions are these
- Given that code, will POSTERR indeed get control on an error?
- The POST documentation documents two error codes, 4 and 8. Will they get
passed to POSTERR? Where?

Yes, I have RTFM but the FM is showing the effects of years of somewhat
piecemeal revisions.

Thanks,

Charles

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Jim Mulder
2018-10-09 02:31:01 UTC
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POSTERR will get control when an abend occurs under the XMPOST
SRB in the target address space. Since you specified MEMREL=NO,
POSTERR will get control under an SRB running in ASID 1.

The return codes 4 and 8 are only for LINKAGE=SYSTEM, so
they are not relevant to your LINKAGE=BRANCH request. They
are return codes in R15 from POST. They are not passed to the ERRET.

For LINKAGE=SYSTEM, return code 8 indicates that the POST is
being done asynchronously (under an SRB in the target address space),
and that ERRET will not be used if an abend occurs under the SRB.
The book doesn't say when you would get return code 8 instead of 4,
but I see in the code that 4 is used when the POST is issued in PSW key
0-7, and 8 is used when the POST is issued in PSW key 8-15.
So it seems that effectively, ERRET is ignored for LINKAGE=SYSTEM
cross-memeory POSTs issue in PSW key 8-15.
I don't know why that was done, but it has been that way since the
introduction of LINKAGE=SYSTEM in MVS/ESA SP3.1.0.

Jim Mulder z/OS Diagnosis, Design, Development, Test IBM Corp.
Poughkeepsie NY
Date: 10/08/2018 10:01 PM
Subject: Cross-memory POST ERRET and return codes
Pursuant to a recent thread here I am converting a cross-memory POST to
use
IEAMSXMP instead. However ... I still need to support older systems
without
IEAMSXMP support, so I will be dual-pathing the existing POST. I got to
looking at code that I have not examined in several years, and I am
trying
to determine exactly what is or should be going on. It runs without
apparent
errors, so this is kind of a theoretical question, not "please help me
with
this error." Here's the POST
POST (R3),LINKAGE=BRANCH,ASCB=(R2),ERRET=POSTERR,MEMREL=NO
The questions are these
- Given that code, will POSTERR indeed get control on an error?
- The POST documentation documents two error codes, 4 and 8. Will they
get
passed to POSTERR? Where?
Yes, I have RTFM but the FM is showing the effects of years of somewhat
piecemeal revisions.
Thanks,
Charles
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Charles Mills
2018-10-09 13:46:29 UTC
Permalink
@Jim, thanks. A couple of follow-ups if I may.

- What is the proper return from an XMPOST ERRET routine? BR 14? I don't see
anything in the docs.

- Would an XMPOST LINKAGE=BRANCH ERRET routine get passed the ABEND code?
Where?

Charles


-----Original Message-----
From: IBM Mainframe Discussion List [mailto:IBM-***@LISTSERV.UA.EDU] On
Behalf Of Jim Mulder
Sent: Monday, October 8, 2018 7:31 PM
To: IBM-***@LISTSERV.UA.EDU
Subject: Re: Cross-memory POST ERRET and return codes

POSTERR will get control when an abend occurs under the XMPOST
SRB in the target address space. Since you specified MEMREL=NO,
POSTERR will get control under an SRB running in ASID 1.

The return codes 4 and 8 are only for LINKAGE=SYSTEM, so
they are not relevant to your LINKAGE=BRANCH request. They
are return codes in R15 from POST. They are not passed to the ERRET.

For LINKAGE=SYSTEM, return code 8 indicates that the POST is
being done asynchronously (under an SRB in the target address space),
and that ERRET will not be used if an abend occurs under the SRB.
The book doesn't say when you would get return code 8 instead of 4,
but I see in the code that 4 is used when the POST is issued in PSW key
0-7, and 8 is used when the POST is issued in PSW key 8-15.
So it seems that effectively, ERRET is ignored for LINKAGE=SYSTEM
cross-memeory POSTs issue in PSW key 8-15.
I don't know why that was done, but it has been that way since the
introduction of LINKAGE=SYSTEM in MVS/ESA SP3.1.0.

Jim Mulder z/OS Diagnosis, Design, Development, Test IBM Corp.
Poughkeepsie NY

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Binyamin Dissen
2018-10-10 08:47:45 UTC
Permalink
On Mon, 8 Oct 2018 15:40:40 -0700 Charles Mills <***@MCN.ORG> wrote:

:>Pursuant to a recent thread here I am converting a cross-memory POST to use
:>IEAMSXMP instead. However ... I still need to support older systems without
:>IEAMSXMP support, so I will be dual-pathing the existing POST. I got to
:>looking at code that I have not examined in several years, and I am trying
:>to determine exactly what is or should be going on. It runs without apparent
:>errors, so this is kind of a theoretical question, not "please help me with
:>this error." Here's the POST

:>POST (R3),LINKAGE=BRANCH,ASCB=(R2),ERRET=POSTERR,MEMREL=NO

:>The questions are these
:>- Given that code, will POSTERR indeed get control on an error?
:>- The POST documentation documents two error codes, 4 and 8. Will they get
:>passed to POSTERR? Where?

:>Yes, I have RTFM but the FM is showing the effects of years of somewhat
:>piecemeal revisions.

I have never truly coded a post error routine (always use CVTBRET).

Consider what must be done if a POST failed, which requires determining the
reasons why the POST failed. In the vast majority of cases I would be running
primary=target and will attempt a quick post first.

1. The target memory terminated

Nothing to do. The RESMGR routines will clean it up.

2. The address is invalid or in the wrong key

The quickpost will catch it.

Also, one must consider the case which posterr will not catch, that is the
storage is reallocated.

Either way, the issues remains - what will you do if the post fails?

--
Binyamin Dissen <***@dissensoftware.com>
http://www.dissensoftware.com

Director, Dissen Software, Bar & Grill - Israel


Should you use the mailblocks package and expect a response from me,
you should preauthorize the dissensoftware.com domain.

I very rarely bother responding to challenge/response systems,
especially those from irresponsible companies.

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Charles Mills
2018-10-10 12:24:18 UTC
Permalink
Post by Binyamin Dissen
Either way, the issues remains - what will you do if the post fails?
Attempt to record the error for an independent process that will ultimately
log it.

Seriously, it's good point, and true for all software recovery: "you're
already hosed up and in some unknown situation that you did not anticipate
-- so now what do you do?"

But you can't just ignore errors.

Charles

-----Original Message-----
From: IBM Mainframe Discussion List [mailto:IBM-***@LISTSERV.UA.EDU] On
Behalf Of Binyamin Dissen
Sent: Wednesday, October 10, 2018 1:48 AM
To: IBM-***@LISTSERV.UA.EDU
Subject: Re: Cross-memory POST ERRET and return codes

On Mon, 8 Oct 2018 15:40:40 -0700 Charles Mills <***@MCN.ORG> wrote:

:>Pursuant to a recent thread here I am converting a cross-memory POST to
use
:>IEAMSXMP instead. However ... I still need to support older systems
without
:>IEAMSXMP support, so I will be dual-pathing the existing POST. I got to
:>looking at code that I have not examined in several years, and I am trying
:>to determine exactly what is or should be going on. It runs without
apparent
:>errors, so this is kind of a theoretical question, not "please help me
with
:>this error." Here's the POST

:>POST (R3),LINKAGE=BRANCH,ASCB=(R2),ERRET=POSTERR,MEMREL=NO

:>The questions are these
:>- Given that code, will POSTERR indeed get control on an error?
:>- The POST documentation documents two error codes, 4 and 8. Will they get
:>passed to POSTERR? Where?

:>Yes, I have RTFM but the FM is showing the effects of years of somewhat
:>piecemeal revisions.

I have never truly coded a post error routine (always use CVTBRET).

Consider what must be done if a POST failed, which requires determining the
reasons why the POST failed. In the vast majority of cases I would be
running
primary=target and will attempt a quick post first.

1. The target memory terminated

Nothing to do. The RESMGR routines will clean it up.

2. The address is invalid or in the wrong key

The quickpost will catch it.

Also, one must consider the case which posterr will not catch, that is the
storage is reallocated.

Either way, the issues remains - what will you do if the post fails?

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Seymour J Metz
2018-10-10 18:18:07 UTC
Permalink
You might want to create, e.g., a dump, a logrec record, a trace record.


--
Shmuel (Seymour J.) Metz
http://mason.gmu.edu/~smetz3

________________________________________
From: IBM Mainframe Discussion List <IBM-***@listserv.ua.edu> on behalf of Binyamin Dissen <***@DISSENSOFTWARE.COM>
Sent: Wednesday, October 10, 2018 4:47 AM
To: IBM-***@listserv.ua.edu
Subject: Re: Cross-memory POST ERRET and return codes

On Mon, 8 Oct 2018 15:40:40 -0700 Charles Mills <***@MCN.ORG> wrote:

:>Pursuant to a recent thread here I am converting a cross-memory POST to use
:>IEAMSXMP instead. However ... I still need to support older systems without
:>IEAMSXMP support, so I will be dual-pathing the existing POST. I got to
:>looking at code that I have not examined in several years, and I am trying
:>to determine exactly what is or should be going on. It runs without apparent
:>errors, so this is kind of a theoretical question, not "please help me with
:>this error." Here's the POST

:>POST (R3),LINKAGE=BRANCH,ASCB=(R2),ERRET=POSTERR,MEMREL=NO

:>The questions are these
:>- Given that code, will POSTERR indeed get control on an error?
:>- The POST documentation documents two error codes, 4 and 8. Will they get
:>passed to POSTERR? Where?

:>Yes, I have RTFM but the FM is showing the effects of years of somewhat
:>piecemeal revisions.

I have never truly coded a post error routine (always use CVTBRET).

Consider what must be done if a POST failed, which requires determining the
reasons why the POST failed. In the vast majority of cases I would be running
primary=target and will attempt a quick post first.

1. The target memory terminated

Nothing to do. The RESMGR routines will clean it up.

2. The address is invalid or in the wrong key

The quickpost will catch it.

Also, one must consider the case which posterr will not catch, that is the
storage is reallocated.

Either way, the issues remains - what will you do if the post fails?

--
Binyamin Dissen <***@dissensoftware.com>
http://secure-web.cisco.com/12ynt5-AyJzto-9-K3Ok8ZRBGSnzPTp-BL4luptrhxENqlBFwW8G7Pit_KsZ7yKArf6mPnT9EKxi33eq2HHMBgMnWMW5nxN7QmjSdoxDsaiVv443xXIDdhUp3_hYYZLpQMqn6e37TD2dq_zxS8HnnSYaJs5GLVlm6gYwzlaR5OdI1Gd6KSiN2xt6uhqHADhgIXzSgMNhi_edNo4bX2VPvSyJfMnjb3MBYJyPpKsvSqSfTtpf5Zw42MRfiQoe5mmcKRBzewDbFey-vkghZcykQRC7yf2JCX99dsTRbycHMnvZhnfmkguS_c7dokeDFJi_AT4HaP1XylfDmljb_Z9zIv-kFpTs7oXQDMoEmr4rNJj_xFW1orHCdKsBYkFp3fFw8YXjyxN7czYexe_pmKaJJVHIf-oyNn18rcm8Xt-bOhd7pBApUv5SjEJohxfJWiLUR/http%3A%2F%2Fwww.dissensoftware.com

Director, Dissen Software, Bar & Grill - Israel


Should you use the mailblocks package and expect a response from me,
you should preauthorize the dissensoftware.com domain.

I very rarely bother responding to challenge/response systems,
especially those from irresponsible companies.

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Charles Mills
2018-10-10 22:52:48 UTC
Permalink
The POSTing code has a partner started task (that it is trying to POST). If
the partner STC has gone away, then the problem is whatever made the STC go
away, not the POST failing; the POST failing is just an inevitable symptom.
If the STC is still there, we put the error code where the STC will find it
(albeit eventually, not as the result of a POST) and log it where it logs
things. I'm pretty happy with that design.

The POSTing code is running sometimes as an SRB and sometimes with locks
held, so the options for logging things directly are limited. Not
nonexistent, but limited.

Charles


-----Original Message-----
From: IBM Mainframe Discussion List [mailto:IBM-***@LISTSERV.UA.EDU] On
Behalf Of Seymour J Metz
Sent: Wednesday, October 10, 2018 11:18 AM
To: IBM-***@LISTSERV.UA.EDU
Subject: Re: Cross-memory POST ERRET and return codes

You might want to create, e.g., a dump, a logrec record, a trace record.

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Peter Relson
2018-10-10 12:14:40 UTC
Permalink
<snip>
- What is the proper return from an XMPOST ERRET routine? BR 14? I don't
see
anything in the docs.
</snip>
You're really asking that? Yes, BR 14 or, I suppose, "return to the
address provided in register 14 by whatever mechanism you have chosen to
do that".

<snip>
- Would an XMPOST LINKAGE=BRANCH ERRET routine get passed the ABEND code?
Where?
</snip>
The register (and environmental) information shown for "When
LINKAGE=SYSTEM is specified" apply also to "When LINKAGE=SYSTEM is not
specified".

Specifically to your question, register 3 which will contain " system
completion code that indicates why the POST request failed"

I have asked that this doc be corrected to show that the register and
environmental info applies to both cases.

Peter Relson
z/OS Core Technology Design


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